CNNUC_1

Team: Rafael Domínguez-Castro, Servando Espejo Meana, Angel Rodríguez-Vázquez and Ricardo Carmona Galán

Date: 1994

This is the first completely programmable Cellular Neural Network chip that can be used in a general purpose fashion. It contain an array of 32x32 mixed signal processors which can perform any operation included in the CNN paradigm [Rosk93] and with low resolution (6-7 bits).

This chip consists of an array of 32x32 identical cells, which are loaded with the same weight control. This is similar to the SIMD (Single Instruction Multiple Data) architecture in digital circuits.

A modified version of the original CNN model has been used [Espe94a]. This model has properties which are very similar to those of the original one, results in higher area and power efficiency, and is more tolerant to process parameter variations.

A hybrid strategy which combines the advantages of analog and digital programmability [Espe94b] has been used to control the programmed values of CNN coefficients. This approach is based on a combined use of analog-programmable multipliers within the cells and of digital control signals from the outside of the cell array. The interface circuitry consists of several identical blocks, one for each programmable parameter in the network. The functionality of each interface blocks is that of a nonlinear D/A converter, and its implementation follows the adaptive architecture shown in Fig 2, in which the analog weight signal adapts its value until the scaling factor of the analog- and digitally-controlled multipliers coincide [Espe94b].

This approach merges most of the advantages of digitally- and analog-programmed multipliers, achieving low areas and a reduced number of control lines, simplifying the control of the weight values, and eliminating their sensitivity to global process parameter variations. In addition, it allows the realization of the APR [Rosk93] using a digital RAM memory.

Every cell incorporates a photosensitive device, which allows the system to be optically initialized. Electrical initialization is also possible, while output image is always downloaded in electrical form. Input and output images are assumed to be binary in every case.

The digital circuitry at each cell includes a four-bit static memory (LLM), a completely programmable two-input digital gate (LLU), and initialization and control circuitry (LCCU) for many different operations. Memory contents can be moved from one location to another. The four-bit memory at each cell allows the network to store four complete images. Two additional "read-only-memories" with fixed +1 and 1 values are also available. Any memory can be used as input U or as initial conditions X(0) of the network.

More details can be found in [Domi94].

References:

1. [Rosk93] T. Roska and L.O. Chua: "The CNN Universal Machine: An Analogic Array Computer", IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol., 40, No.-3, March 1993.
2. [Chua93] L.O. Chua, T. Roska and P.L. Venetianer: "The CNN is Universal as the Turing Machine". IEEE Trans. Circuits and Systems I: Fundamental Theory and Applications, Vol. 40, pp 289-291, April 1993.
3. [Domi94] R. Domínguez-Castro, S. Espejo, A. Rodríguez-Vázquez, and R. Carmona: "A CNN Universal Chip in CMOS Technology". Proceedings of the 3rd International Workshop on Cellular Neural Networks and their Applications,pp. 91-96. Rome, December 1994.
4. [Espe94a] S. Espejo, A. Rodríguez-Vázquez, R. Domínguez-Castro, and R. Carmona: "Convergence and Stability of the FSR CNN Model". Proceedings of the 3rd International Workshop on Cellular Neural Networks and their Applications,pp. 411-416. Rome, December 1994.
5. [Espe94b] S. Espejo, R. Domínguez-Castro, A. Rodríguez-Vázquez, and R. Carmona: "Weight-Control Strategy for Programmable CNN Chips". Proceedings of the 3rd International Workshop on Cellular Neural Networks and their Applications,pp. 405-410. Rome, December 1994.

Images List:

• Figure 1: Chip Microphotograph

• Figure 2: Architecture of the D/A interface circuitry required for the hybrid-control approach

• Figure 3: a) Chip Microphotograph, b) Cell Microphotograph

• Figure 4: Microphotograph (a) and measured output of an adaptive stage: b) differential weight voltages; c) difference of the weight voltages.