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A 16.4bit, 9.6kSample/s 1.71mW CMOS  
Modulator
Team: Fernando Medeiro, Belén
Pérez-Verdú and Angel Rodríguez-Vázquez
Date: 1997
| Physical Data |
- 0.7µ m CMOS n-well, single-poly,
double metal
- 0.42mm2
(excluding pads)
- 220 transistors
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Electrical Data |
- Switched-Capacitor fully-differential
circuitry
- 5-V (4-V minimum) supply @ 1.71mW
- 2.56-MHz clock frequency (on-chip phase
generation)
- 9.6-kSample/s output rate (4.8-kHz bandwidth)
- 100.2dB dynamic range (16.4bit)
- 94.2dB SNR-peak
- 1.25-V peak input signal
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| Design Technique: |
- Automatized modulator and cell sizing
- Analog full-custom, digital semi-custom
- Switched-Capacitor circuits:
- Optimized integrator weights for
minimum output swing and dynamic requirements
- Integrators with phase delay feed-through
compensation
- Folded-cascode amplifier with static
common-mode feedback net
- Chopper compensation of the first
amplifier offset and flicker noise
- Fast regenerative latched comparators.
- Layout
- Guard rings, shielding, symmetry.
- Separate A and D supply lines.
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Features and Applications: |
- Optimized
design for minimization of the Figure-of-Merit
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- Used in the
current-front end of an energy metering ASIC
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Designing M
ICs with minimum power consumption and performance specifications (resolution
X speed) at the state-of-the-art edge is a complicated and
time-consuming task. On the one hand, the operation of high-performance
Ms is
commonly limited by non-idealities other than quantization: thermal noise,
incomplete settling, finite opamp-gain, opamp non-linearity, mismatches,
jitter, etc. [Nors96]. On the other, intensive
optimization is needed to map the high-level specifications of Ms
into working ICs. A way to successfully achieve such requirements is to
resort to CAD tools. In particular, all the critical tasks involved in
the design of this modulator (architecture selection, modulator sizing
and cell sizing) were supported by proprietary CAD tools [Mede95]
and completed in only one week by one engineer, while the full-custom
layout of the prototype, which was done manually, took about three weeks.
The results obtained, 16.4-b resolution at 9.6kS/s with a power consumption
of 1.71mW lead to a value of the 
Figure-of-Merit of 2 picojoule, which is one of the lowest reported to
now for CMOS
modulators [Mede97], thus demonstrating the
validity of our methodology.
References:
- [Nors96] S.R.
Norsworthy et al. (eds.): Delta-Sigma Data Converters: Theory, Design
and Simulation. IEEE Press 1996.
- [Mede95] F. Medeiro, B. Pérez-Verdú,
A. Rodríguez-Vázquez and J.L. Huertas: "A Vertically-Integrated
Tool for Automated Design of Sigma-Delta Modulators", IEEE J. of
Solid-State C. Vol.30, pp. 762-772, July 1995.
- [Mede97] F. Medeiro, B. Pérez-Verdú,
J. M. de la Rosa, A. Rodríguez-Vázquez. "Using CAD
tools for shortening the design cycle of high-performance sigma-delta
modulators: a 16.4 Bit, 9.6 KHz, 1.71mW M
in CMOS 0.7µ m technology", International journal of circuit
theory and applications, Vol. 25, p. 319-334, 1997.
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