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CNNUC_3

Team: G. Liñán, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez

Date: 1999

 

Physical Data
  • 0.5 µ m CMOS Twin-Well, Single-Poly, Triple Metal Technology.
  • ~1.000.000 Transistors (800.000 of them working in analog mode).
  • 87 mm2 (Including pads).
Electrical Data
  • 64x64 array of neurons.
  • Gray-Scale and Binary Image Processing.
  • Gray-Scale, Binary or Optical, input possibilities.
  • Analog Program Register for 32 Templates.
  • Switch Configuration Register for 64 Instructions.
  • 1-1.5W@3.3V Power Consumption.
Design Technique
  • Continuous Time Implementation of the FSR CNN Model.
  • Analog Full Custom Design.
  • One Transistor Synapse Strategy.
  • On-Chip Calibration Structures.
  • Distributed Buffer Topology.
  • Bottom Sampling in the Gray Scale Image. Memories.
  • Programmable Signal and Weight Ranges.
Features and Applications
  • Real Time Image Processing.
  • Video Coding and Segmentation
  • Texture Classification
  • Motion Detection
  • Direct Optical Acquisition of Gray Scale Images.

 

CNNUC_3, consists, basically, of an array of 64x64 identical cells. Its fundamental functionality is to perform CNN operations on 64x64 pixel-arrays (images). The processing is continuous-time and spatially-invariant, with each cell interacting with its nearest neighbors. Feedback and control templates, as well as the offset (or bias) term are programmable with a resolution of eight bits (seven + sign). Input and output pixel values are analog (gray-scale) in general. In addition, specific functions are included for binary (black&white) images, which can also be processed. Image storage, both analog and binary, is available in a spatially-distributed form: each cell is able to store four different greyscale pixel values and four different binary (B&W) pixel values thus allowing a fully-parallel (64 x 64 wide) data-transference between processors and memory.

Fig 2 shows the chip architecture. The prototype incorporates some global-control and programming circuitry located in the periphery of the array. This includes memory for 32 arbitrary sets of CNN coefficients and for 64 arbitrary sets of 35 digital signals that are used as digital instructions to configure properly the cell in order to perform different task ranging from running a CNN process to configure the cell I/O circuitry. These memories can be randomly addressed from the hosting platform once they have been programmed.

The external control is completely digital. The interface has been designed to be easily embedded in conventional digital systems centred around a CPU or a DSP unit. Two bidirectional data-buses, one analog and one digital, are employed for image loading and downloading.

More details about the prototype can be found in [Linan99] and its list of references.

 

References:

  1. [Linan99] G. Liñán, S. Espejo, R. Domínguez-Castro E. Roca and A. Rodríguez-Vázquez. "CNNUC3: A Mixed-Signal 64x64 CNN Universal Chip", Proc of the VII International Conference of Microelectronics for Neural, Fuzzy and Bio-inspired Systems, pp.61-68, Granada, April 1999.

 

Images List:

 

 
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