DETECTORS-1

Team: E. Roca, S. Espejo, R. Domínguez-Castro and A. Rodríguez-Vázquez.

Date: 1997

This design is intended to characterize the different types of visible detectors available in an standard CMOS process, as well as to obtain statistical information on the behaviour of NMOS and PMOS transistors processed on this technology.

Visible detectors

For the characterization of visible detectors, we have included four different types of detectors formed by junction structures available in an standard n-well CMOS process. The first three structures are p/n junction diodes, whereas the last one is a vertical bipolar junction transistor (BJT). Diodes are formed by well/substrate (n-/p-) junctions, source-drain diffusion/substrate (n+/p-) junctions and source-drain diffusion/well (p+/n-) junctions. Vertical p/n/p bipolar junction transistors are obtained by the structure formed by a p+ source-drain diffusion, an n- well and the p- substrate. In the chip we have included both discrete detectors, which are placed at the outer part of the chip, and arrays of 16x16 detectors, which are situated in the central left area of the chip. To access the different elements of each array, three different decoders are used: one for the arrays, a second one for the columns and the last one for the rows.

For the case of discrete diodes, the three different types of devices are included in the chip at least for one size, which is the largest size (100µ m100µ m). One of them is studied in detail to obtain information on both area scaling and perimeter effects by including 4 different sizes (ranging from 100µ m100µ m to minimum size), and one of these sizes is studied for three different perimeters. The last diode is processed for two different sizes and two perimeters for one size. The well/substrate diode includes a n+ contact ring for the largest detector areas to improve the collection of photogenerated carriers. Vertical bipolar transistors are also included in the chip with base areas ranging from the minimum size to 16 times the minimum size.

Arrays of detectors are included in the design to obtain statistical information on the response of the detectors for their future application in imaging cameras. For this reason the areas of the detectors are of minimum size or four times this minimum size, corresponding to usual areas in this type of applications. In some cases, the efficiency of the substrate contact is studied by changing its size and position in the pixel. The size of the substrate contact is important for the design of imaging cameras, since it affects the fill factor (ratio of sensing area to pixel area) of the pixel.

MOS transistors

Arrays of 16x16 MOS transistors have been included in the design to obtain statistical information of the behaviour of these devices. Both NMOS and PMOS transistors have been studied with 3 different aspect ratios for each type of transistor.

Images List:

• Figure 1: Die microphotograph